9DB401CGLF
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB401 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
更新于 2026-08-149DB401CGLF
电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 9DB401 |
| Number of Elements per Chip: | 1 |
| Output Frequency Range: | 50 to 200 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 200 MHz |
| Rad Hard: | No |
9DB401CGLFT
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB401 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
9DB401CGLFT
电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 9DB401 |
| Number of Elements per Chip: | 1 |
| Output Frequency Range: | 50 to 200 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 200 MHz |
| Rad Hard: | No |
9DB801BFLF
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
9DB801BFLF
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | 1 |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 200 MHz |
| Rad Hard: | No |
9DB801BFLFT
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
9DB801BGLF
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
9DB801BGLFT
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
9DB801CFLF
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
9DB801CFLFT
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | 1 |
| Output Frequency Range: | 50 to 200 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 200 MHz |
| Rad Hard: | No |
9DB801CGLF
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | 1 |
| Output Frequency Range: | 50 to 200 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 200 MHz |
| Rad Hard: | No |
9DB801CGLF
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
9DB801CGLFT
电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB801 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
9E4101AFILF
电气特性 Features
| Type: | Programmable PLL Clock Synthesizer |
| Family: | 9E4101 |
| Number of Elements per Chip: | 2 |
| Output Frequency Range: | Up to 400 |
| Operating Temperature: | -40 to 85 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 14.31818 MHz |
| Rad Hard: | No |