更新于 2026-08-14电气特性 Features
| Type: | PLL Clock Buffer |
| Family: | 9DB401 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 50 MHz |
| Maximum Input Frequency: | 400 MHz |
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电气特性 Features
| Rad Hard: | No |
| Family: | R413.808.121 |
电气特性 Features
| Category: | UHF ASK/FSK Receiver |
| Operating Band Frequency: | 431.5 to 436.5 MHz |
| Maximum RF Operating Frequency: | 433 MHz |
| Modulation Technique: | ASK|FSK |
| Operating Supply Voltage: | 5 V |
| Rad Hard: | No |
电气特性 Features
| Minimum Frequency: | 0 GHz |
| Maximum Frequency: | 6 GHz |
| Impedance: | 50 Ohm |
| Maximum Power Rating: | 100 W |
| Connector Type: | SMA |
| Attenuation Tolerance: | ±0.5 dB |
| Maximum Attenuation: | 14(Typ) dB |
| Maximum VSWR: | 1.3 |
| Rad Hard: | No |
| Family: | R411.814.124 |
电气特性 Features
| Rad Hard: | No |
| Family: | R413.803.115 |
电气特性 Features
| Category: | Transceiver |
| Operating Band Frequency: | 2400 to 2483 MHz |
| Maximum RF Operating Frequency: | 2483 MHz |
| Modulation Technique: | FSK |
| Operating Supply Voltage: | 1.8|2.5|3.3 V |
| Rad Hard: | No |