954119DFLF
电气特性 Features
| Type: | Programmable PLL Clock Synthesizer |
| Family: | 954119 |
| Number of Elements per Chip: | 2 |
| Output Frequency Range: | 24 to 400 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 14.31818 MHz |
| Rad Hard: | No |
954119DFLFT
电气特性 Features
| Type: | Programmable PLL Clock Synthesizer |
| Family: | 954119 |
| Number of Elements per Chip: | 2 |
| Output Frequency Range: | 24 to 400 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 14.31818 MHz |
| Rad Hard: | No |
954201BFLF
电气特性 Features
| Type: | Programmable PLL Clock Driver |
| Family: | 954201 |
| Number of Elements per Chip: | Dual |
| Output Frequency Range: | 100 to 400|100|96|48|33.33 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 14.318 MHz |
954201BFLFT
电气特性 Features
| Type: | Programmable PLL Clock Driver |
| Family: | 954201 |
| Number of Elements per Chip: | Dual |
| Output Frequency Range: | 100 to 400|100|96|48|33.33 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 14.318 MHz |
954201BGLF
电气特性 Features
| Type: | Programmable PLL Clock Synthesizer |
| Family: | 954201 |
| Number of Elements per Chip: | 2 |
| Output Frequency Range: | 33.33 to 400 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 14.31818 MHz |
| Rad Hard: | No |
954201BGLFT
电气特性 Features
| Type: | Programmable PLL Clock Synthesizer |
| Family: | 954201 |
| Number of Elements per Chip: | 2 |
| Output Frequency Range: | 33.33 to 400 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 14.31818 MHz |
| Rad Hard: | No |
95V157AGLF
电气特性 Features
| Type: | Zero Delay PLL Clock Driver |
| Family: | 95V157 |
| Number of Elements per Chip: | 1 |
| Operating Temperature: | 0 to 85 °C |
| Operating Supply Voltage: | 2.5 V |
| Rad Hard: | No |
95V157AGLFT
电气特性 Features
| Type: | Zero Delay PLL Clock Driver |
| Family: | 95V157 |
| Number of Elements per Chip: | 1 |
| Operating Temperature: | 0 to 85 °C |
| Operating Supply Voltage: | 2.5 V |
| Rad Hard: | No |
9DB102BFLF
电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 9DB102 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 99 MHz |
| Maximum Input Frequency: | 101 MHz |
9DB102BFLFT
电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 9DB102 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 99 MHz |
| Maximum Input Frequency: | 101 MHz |
9DB102BGILF
电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 9DB102 |
| Number of Elements per Chip: | 1 |
| Operating Temperature: | -40 to 85 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 99 MHz |
| Maximum Input Frequency: | 101 MHz |
| Rad Hard: | No |
9DB102BGLF
电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 9DB102 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 99 MHz |
| Maximum Input Frequency: | 101 MHz |
9DB102BGLFT
电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 9DB102 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 99 MHz |
| Maximum Input Frequency: | 101 MHz |
9DB104BFLF
电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 9DB104 |
| Number of Elements per Chip: | 1 |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 80 MHz |
| Maximum Input Frequency: | 220 MHz |
| Rad Hard: | No |
9DB104BFLFT
电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 9DB104 |
| Number of Elements per Chip: | Single |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 80 MHz |
| Maximum Input Frequency: | 220 MHz |

更新于 2026-08-14