更新于 2026-08-20电气特性 Features
| Type: | Programmable PLL Clock Buffer |
| Family: | CV122 |
| Number of Elements per Chip: | 4 |
| Output Frequency Range: | Up to 400 |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Minimum Input Frequency: | 14.31818 MHz |
| Rad Hard: | No |
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电气特性 Features
| Category: | Receiver |
| Operating Band Frequency: | 902 to 928 MHz |
| Maximum RF Operating Frequency: | 928 MHz |
| Modulation Technique: | ASK|FSK |
| Operating Supply Voltage: | 5 V |
电气特性 Features
| Category: | Receiver |
| Operating Band Frequency: | 8 to 135 MHz |
| Maximum RF Operating Frequency: | 135 MHz |
| Operating Supply Voltage: | 3.3 V |
| Rad Hard: | No |
电气特性 Features
| Number of Bits: | 5 |
| Maximum Frequency: | 2500 MHz |
| Operating Supply Voltage: | 5(Typ) V |
| Rad Hard: | No |
电气特性 Features
| Minimum Frequency: | 2.9 GHz |
| Maximum Frequency: | 3.5 GHz |
| Impedance: | 50 Ohm |
| Maximum Power Rating: | 200 W |
| Connector Type: | SMA |
| Rad Hard: | No |
电气特性 Features
| Category: | Transceiver |
| Operating Band Frequency: | 2405 to 2480 MHz |
| Maximum RF Operating Frequency: | 2480 MHz |
| Modulation Technique: | O-QPSK |
| Operating Supply Voltage: | 2.7 V |
| Rad Hard: | No |