更新于 2026-08-17电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | CY23S05 |
| Number of Elements per Chip: | 1 |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Rad Hard: | No |
相关文章
电气特性 Features
| Category: | Receiver |
| Operating Band Frequency: | 283 to 350|425 to 525|850 to 960 MHz |
| Maximum RF Operating Frequency: | 960 MHz |
| Modulation Technique: | FSK|GFSK|OOK |
| Operating Supply Voltage: | 3 V |
| Rad Hard: | No |
电气特性 Features
| Minimum Frequency: | 0 GHz |
| Maximum Frequency: | 18 GHz |
| Impedance: | 50 Ohm |
| Maximum Power Rating: | 100 W |
| Connector Type: | TNC |
| Attenuation Tolerance: | ±0.6 dB |
| Maximum Attenuation: | 16(Typ) dB |
| Maximum VSWR: | 1.35 |
| Rad Hard: | No |
| Family: | R414.516.161 |
电气特性 Features
| Rad Hard: | No |
| Family: | R416.006.000 |
电气特性 Features
| Minimum Frequency: | 0 GHz |
| Maximum Frequency: | 2 GHz |
| Impedance: | 50 Ohm |
| Connector Type: | SMA |
| Maximum Attenuation: | 10(Typ) dB |
| Maximum VSWR: | 1.25 |
| Rad Hard: | No |
| Family: | R417.910.118 |
电气特性 Features
| Number of Bits: | 5 |
| Maximum Frequency: | 40000 MHz |
| Rad Hard: | No |