更新于 2026-08-17电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | CY23S05 |
| Number of Elements per Chip: | 1 |
| Operating Supply Voltage: | 3.3 V |
| Rad Hard: | No |
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电气特性 Features
| Category: | Transceiver |
| Operating Band Frequency: | 300 to 450 MHz |
| Maximum RF Operating Frequency: | 450 MHz |
| Modulation Technique: | ASK|FSK|OOK |
| Operating Supply Voltage: | 2.7|5 V |
| Rad Hard: | No |
电气特性 Features
| Number of Bits: | 5 |
| Maximum Frequency: | 2000 MHz |
| Operating Supply Voltage: | 5(Typ) V |
| Rad Hard: | No |
电气特性 Features
| Category: | Transceiver |
| Operating Band Frequency: | 80 to 960 MHz |
| Maximum RF Operating Frequency: | 960 MHz |
| Modulation Technique: | FSK|GFSK|MSK |
| Operating Supply Voltage: | 3 V |
| Rad Hard: | No |
电气特性 Features
| Category: | Transceiver |
| Operating Band Frequency: | 850 to 950 MHz |
| Maximum RF Operating Frequency: | 950 MHz |
| Operating Supply Voltage: | 2.5|3.3 V |
| Rad Hard: | No |
电气特性 Features
| Rad Hard: | No |
| Family: | R413.809.121 |