更新于 2026-08-17电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | CY23S09 |
| Number of Elements per Chip: | 1 |
| Output Frequency Range: | 10 to 133.33 MHz |
| Operating Temperature: | 0 to 70 °C |
| Operating Supply Voltage: | 3.3 V |
| Rad Hard: | No |
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电气特性 Features
| Category: | Receiver |
| Operating Band Frequency: | 302 to 870 MHz |
| Maximum RF Operating Frequency: | 870 MHz |
| Modulation Technique: | ASK/FSK |
| Operating Supply Voltage: | 3.3|5 V |
| Rad Hard: | No |
电气特性 Features
| Category: | Receiver |
| Operating Band Frequency: | 64 to 108 MHz |
| Maximum RF Operating Frequency: | 108 MHz |
| Modulation Technique: | AM|FM |
| Operating Supply Voltage: | 1.8|3.3 V |
| Rad Hard: | No |
电气特性 Features
| Category: | Transceiver |
| Operating Band Frequency: | 300 to 500 MHz |
| Maximum RF Operating Frequency: | 500 MHz |
| Modulation Technique: | FSK |
| Operating Supply Voltage: | 3 V |
| Rad Hard: | No |
电气特性 Features
| Minimum Frequency: | 0 GHz |
| Maximum Frequency: | 18 GHz |
| Impedance: | 50 Ohm |
| Maximum Power Rating: | 14 W |
| Connector Type: | SMA |
| Attenuation Tolerance: | ±1 dB |
| Maximum Attenuation: | 14(Typ) dB |
| Maximum VSWR: | 1.35 |
| Rad Hard: | No |
| Family: | R411.814.121 |
电气特性 Features
| Category: | Receiver |
| Operating Band Frequency: | 315|433.92 MHz |
| Maximum RF Operating Frequency: | 433.92 MHz |
| Modulation Technique: | FSK |
| Operating Supply Voltage: | 3.3 V |
| Rad Hard: | No |