更新于 2026-08-10电气特性 Features
| Type: | Zero Delay PLL Clock Buffer |
| Family: | 2309 |
| Number of Elements per Chip: | 1 |
| Output Frequency Range: | 10 to 133 MHz |
| Operating Temperature: | -40 to 85 °C |
| Operating Supply Voltage: | 3.3 V |
| Rad Hard: | No |
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电气特性 Features
| Category: | Receiver |
| Operating Band Frequency: | 433.72 to 434.12 MHz |
| Maximum RF Operating Frequency: | 434.12 MHz |
| Modulation Technique: | OOK |
| Operating Supply Voltage: | 3.3 V |
| Rad Hard: | No |
电气特性 Features
| Minimum Frequency: | 0 GHz |
| Maximum Frequency: | 2 GHz |
| Impedance: | 50 Ohm |
| Connector Type: | SMA |
| Maximum Attenuation: | 6(Typ) dB |
| Maximum VSWR: | 1.25 |
| Rad Hard: | No |
| Family: | R417.906.118 |
电气特性 Features
| Category: | Transceiver |
| Maximum RF Operating Frequency: | 915 MHz |
| Modulation Technique: | ASK|FSK |
| Operating Supply Voltage: | 2.5|3.3|5 V |
电气特性 Features
| Number of Bits: | 5 |
| Maximum Frequency: | 4000 MHz |
| Operating Supply Voltage: | 2.7 to 5.5 V |
电气特性 Features
| Category: | Transceiver |
| Operating Band Frequency: | 2400 to 2524 MHz |
| Maximum RF Operating Frequency: | 2524 MHz |
| Modulation Technique: | GFSK |
| Operating Supply Voltage: | 3 V |
| Rad Hard: | No |